The present invention relates to a semiconductor memory device and a process for manufacturing the same and in particular to a semiconductor memory device which is suitable for a non-volatile memory in which a silicide layer is formed on the surface of the control gate and a process for manufacturing the same.
Although LOCOS (Local Oxidation of Silicon) process has heretofore been used for insulating and isolating cells from each other in the floating type volatile memories reduction in cell size is difficult to achieve since the isolation width is large and the isolation breakdown voltage is low due to the presence of bird""s beaks in this process. Therefore, in order to achieve reduction in the cell size, a manufacturing process in which STI (Shallow Trench Isolation) process is applied to non-volatile memories has been proposed.
In this process, a trench is formed by digging a silicon substrate at an element isolating region and an insulator is embedded in this trench. This process will now be described in brief. A buffer oxide layer and polysilicon layer each having a predetermined thickness are laminated on a silicon substrate and an oxide layer is formed thereon by a CVD process. Then, a resist having a given pattern is formed thereon. The oxide layer, polysilicon layer and buffer oxide layer are successively etched using the resist pattern as a mask. After the resist pattern has been removed, the trench is formed by etching the silicon substrate using the oxide layer as a mask. Then after embedding the insulator in the trench, element isolating regions are formed by performing flattening of the substrate.
Although, the cell size of the memory can be reduced by adopting the foregoing process, a problem occurs that the size of a step difference increases in association with the reduction in cell size when a floating gate and control gate, which are to be laminated to each other are formed.
Since high speed operation is not required when a non-volatile memory is singly used, the resistance of the gate material does not give rise to a great extent. However, in a logic-hybrid memory in which logic circuits are incorporated in the non-volatile memory, an enhancement in the operational speed of the memory is demanded in association with the speeding-up of the logic circuits.
In order to achieve the speeding-up of the operation of the memory, it is important to make the conduction of signal faster by lowering the resistance of polysilicon which is used as a gate material. One method to do this may include lowering of the specific resistivity by doping the polysilicon with, for example, a dopant such as phosphorus. If the gate layer has a thin thickness, the dopant such as phosphorus could penetrate through the gate resulting in doping a dielectric layer which is disposed below the gate, so that the dielectric characteristics will deteriorate.
A method of lowering the resistance of the gate by silicidation of the surface of the gate material including polysilicon is disclosed in Japanese Patent Kokai Publication JP-A-9-283643. A conventional silicidation of polysilicon will now be described with reference to FIGS. 11 through 13. FIGS. 11 and 12 schematically show the sequence of manufacturing process and are divided for convenience of drawing.
First, as shown in FIG. 11(a), a trench element isolating region 2 is formed on a silicon substrate 1 in accordance with the above-mentioned process and after a gate oxide layer 3 has been formed, polysilicon intended to become a floating gate 4 is deposited thereon (refer to FIG. 11(b)). Then, a resist pattern having a given configuration is formed and a floating gate 4 is formed as shown in FIG. 11(c) by etching the resist pattern.
After an interlayer insulating layer (termed herein as xe2x80x9cdielectricxe2x80x9d) such as ONO (Oxide-Nitride-Oxide) layer 5 has been formed in such a manner that it covers the isolated floating gate 4, polysilicon which will become a control gate 8 is deposited and is patterned to a given configuration (refer to FIG. 11(e)).
Subsequently, in order to form a sidewall 14 on the lateral wall (not shown) of the control gate, growth and etching back of a sidewall oxide layer 9 is performed (refer to FIGS. 12(f) and (g)). At this time, the control gate will be formed with a depression 13 due to a step difference in association with reduction in spacing of the floating gate 4. The sidewall oxide layer 9 is formed such that it is embedded in the depression 13.
When a titanium silicide layer 10 is formed on the upper face of the control gate 8 by a sputtering process as shown in FIG. 12(h), the silicide layer 10 is deposited on the sidewall oxide layer 9a since a sidewall oxide layer 9 is embedded in the above-mentioned depression 13. Then, etching back of excess titanium is conducted as shown in FIG. 12(i) to remove the silicide layer 10 which has been sputtered on an unwanted region. A structure which is shown in FIG. 13(a) is obtained by subsequently forming the interlayer dielectric 11 and a contact 12.
In the course of intensive investigations toward the present invention the following problems have been encountered.
If the titanium silicide layer 10 can be uniformly formed over the upper layer of the control gate 8 by adopting the above-mentioned structure, the operation speed of the control gate 8 could be made faster. In accordance with the above-mentioned method, however, the sidewall oxide layer 9 is embedded in the depression 13 formed in the control gate 8 and the silicide layer 10 is deposited upon the sidewall oxide layer 9a. Accordingly, the silicide layer 10 which is deposited upon the above-mentioned sidewall oxide layer 9a will be separated (peeled off) when the excess titanium is etched back.
If there is even one separated point, reduction in resistance of the control gate 8 can not be achieved. This disadvantage becomes remarkable as the spacing between the floating gates 4 become smaller. In a typical non-volatile memory, the thickness of the layer including the gate oxide layer 3, floating gate 4 and ONO layer 5 is about 0.15 xcexcm whereas the spacing between the floating gates 4 is as narrow as about 0.3 xcexcm. The control gate 4 is formed with the depression 13 having a shape which is shown in the drawing. Fracture of the silicide layer 10 may take place at this portion.
The present invention has been achieved to overcome the above-mentioned problem. It is a primary object of the present invention to provide a semiconductor memory device in which no separation of the silicide layer occurs, which is formed on the control gate and a process for manufacturing the same.
In order to accomplish the above-mentioned object, in a first aspect of the present invention, there is provided a semiconductor memory device having a silicon substrate on which a gate dielectric layer, floating gate, interlayer dielectric and a control gate are successively laminated and in which a silicide layer is formed on the surface of the control gate, in which a sidewall which is formed of a plurality members is disposed on the lateral wall of the floating gate.
In a second aspect of the present invention, there is provided a semiconductor memory device having a silicon substrate on which a gate dielectric layer, floating gate, interlayer dielectric and a control gate are successively laminated and in which a silicide layer is formed on the surface of the control gate, in which a sidewall which is formed of a plurality members containing an electrically conductive material is disposed on the lateral wall of the floating gate.
In a third aspect of the present invention, there is provided a semiconductor memory device having a silicon substrate on which a gate dielectric layer, floating gate, inter layer dielectric and a control gate are successively laminated and in which a silicide layer is formed on the surface of the control gate, in which a sidewall comprising a first and second members which are in contact with the lateral wall of the floating gate is disposed on the lateral wall of the floating gate and in that the first member functions as an etching stop for the second member.
In a fourth aspect of the present invention, there is provided a process for manufacturing a semiconductor memory device. The process for manufacturing a semiconductor memory device having a silicon substrate on which a gate dielectric layer, floating gate, interlayer dielectric and a control gate are successively laminated and in which a silicide layer is formed on the surface of the control gate, in which a sidewall which is formed of a plurality members is disposed as a sidewall of the floating gate.
In a fifth aspect of the present invention, there is provided a process for manufacturing a semiconductor memory devices comprising the steps of: (a) forming a gate dielectric layer on a silicon substrate; (b) forming a floating gate on the gate dielectric layer; (c) causing a first member to grow as a film on at least upper and lateral sides of the floating gate; (d) depositing a second member which will become a sidewall over an entire surface of the silicon substrate; (e) forming the sidewall by etching back the second member using the first member as an etching stop so that the second member remains only on the lateral wall of the floating gate; (f) removing the first member which is exposed on an upper surface of the floating gate; (g) causing an interlayer dielectric to grow as a film on upper surfaces of the floating gate, the first and second members; (h) forming a control gate on the interlayer dielectric; and (i) forming a silicide layer on a surface of the control gate.